With the 2022 Flash Reminiscence Summit going down this week, not solely is there a slew of solid-state storage bulletins within the pipe over the approaching days, however the present can be more and more a preferred venue for discussing I/O and interconnect developments as effectively. Kicking issues off on that entrance, this afternoon the OpenCAPI and CXL consortiums are issuing a joint announcement that the 2 teams might be becoming a member of forces, with the OpenCAPI normal and the consortium’s property being transferred to the CXL consortium. With this integration, CXL is about to grow to be the dominant CPU-to-device interconnect normal, as nearly all main producers at the moment are backing the usual, and competing requirements have bowed out of the race and been absorbed by CXL.
Pre-dating CXL by just a few years, OpenCAPI was one of the earlier standards for a cache-coherent CPU interconnect. The usual, backed by AMD, Xilinx, and IBM, amongst others, was an extension of IBM’s present Coherent Accelerator Processor Interface (CAPI) expertise, opening it as much as the remainder of the trade and putting its management below an trade consortium. Within the final six years, OpenCAPI has seen a modest quantity of use, most notably being applied in IBM’s POWER9 processor household. Like comparable CPU-to-device interconnect requirements, OpenCAPI was primarily an utility extension on high of present excessive pace I/O requirements, including issues like cache-coherency and sooner (decrease latency) entry modes in order that CPUs and accelerators may work collectively extra intently regardless of their bodily disaggregation.
However, as one in all a number of competing requirements tackling this drawback, OpenCAPI by no means fairly caught fireplace within the trade. Born from IBM, IBM was its largest person at a time when IBM’s share within the server house has been on the decline. And even consortium members on the rise, equivalent to AMD, ended up skipping on the expertise, leveraging their very own Infinity Material structure for AMD server CPU/GPU connectivity, for instance. This has left OpenCAPI with out a robust champion – and with out a sizable userbase to maintain issues transferring ahead.
In the end, the will of the broader trade to consolidate behind a single interconnect normal – for the sake of each producers and prospects – has introduced the interconnect wars to a head. And with Compute Categorical Hyperlink (CXL) rapidly turning into the clear winner, the OpenCAPI consortium is turning into the newest interconnect requirements physique to bow out and grow to be absorbed by CXL.
Below the phrases of the proposed deal – pending approval by the required events – the OpenCAPI consortium’s property and requirements might be transferred to the CXL consortium. This would come with all the related expertise from OpenCAPI, in addition to the group’s lesser-known Open Memory Interface (OMI) standard, which allowed for attaching DRAM to a system over OpenCAPI’s bodily bus. In essence, the CXL consortium can be absorbing OpenCAPI; and whereas they gained’t be persevering with its improvement for apparent causes, the switch implies that any helpful applied sciences from OpenCAPI might be built-in into future variations of CXL, strengthening the general ecosystem.
With the sublimation of OpenCAPI into CXL, this leaves the Intel-backed normal as dominant interconnect normal – and the de facto normal for the trade going ahead. The competing Gen-Z standard was equally absorbed into CXL earlier this yr, and the CCIX normal has been left behind, with its main backers becoming a member of the CXL consortium in recent times. So even with the primary CXL-enabled CPUs not transport fairly but, at this level CXL has cleared the neighborhood, because it had been, turning into the only real remaining server CPU interconnect normal for every part from accelerator I/O (CXL.io) to reminiscence growth over the PCIe bus.
