The studies about an inadequate provide of compute GPUs used for synthetic intelligence (AI) and high-performance computing (HPC) servers turned widespread in current months as demand for GPUs to energy generative AI purposes exploded. TSMC admits that the largest compute GPU provide bottleneck is its chip-on-wafer-on-substrate (CoWoS) packaging capability, as it’s utilized by just about everybody within the AI and HPC enterprise. The corporate is increasing CoWoS capability however believes that its scarcity will persist for 1.5 years.
“It just isn’t the scarcity of AI chips,” stated Mark Liu, the chairman of TSMC, in a dialog with Nikkei. “It is the scarcity of our CoWoS capability. […] At the moment, we can’t fulfill 100% of our prospects’ wants, however we attempt to help about 80%. We predict this can be a momentary phenomenon. After our enlargement of [advanced chip packaging capacity], it needs to be alleviated in a single and a half years.“
TSMC at present produces the overwhelming majority of processors that energy fashionable AI companies, together with compute GPUs (reminiscent of AMD’s Intuition MI250 and NVIDIA’s A100 and H100), FPGAs, and specialised ASICs from corporations like d-Matrix and Tenstorrent in addition to proprietary processors from cloud service suppliers, reminiscent of AWS’s Trainium and Inferentia in addition to Google’s TPU.
It’s noteworthy that compute GPUs, FPGAs, and accelerators from CSPs all use HBM reminiscence to get the very best bandwidth attainable and use TSMC’s interposer-based chip-on-wafer-on-substrate packaging. Whereas conventional outsourced semiconductor meeting and take a look at (OSAT) corporations like ASE and Amkor additionally provide comparable packaging applied sciences, it seems to be like TSMC is getting the lion’s share of the orders, which is why it may well barely meet demand for its packaging companies.
Business analysts consider that OSATs are much less motivated to supply superior packaging companies as a result of it requires them to speculate hefty quantities of capital and poses extra monetary dangers than conventional packaging. For instance, if one thing goes improper with a mainstream processor that sits on an natural substrate, an OSAT loses just one chip, whereas if one thing goes improper with a bundle carrying 4 chiplets and eight HBM reminiscence stacks, the corporate loses a whole lot if not 1000’s of {dollars}. Since OSATs don’t get substantial margins making these chiplets, such dangers decelerate the enlargement of superior packaging capability at OSATs, although superior packaging prices considerably more cash than conventional packaging.
Similar to its trade friends, TSMC is spending billions on upcoming superior packaging services. For instance, the corporate just lately introduced plans to spend nearly $2.9 billion on a packaging fab that’s rumored to come back on-line in 2027.
“We’re growing our capability as rapidly as attainable,” stated C.C. Wei, chief govt of TSMC, on the firm’s earnings name earlier this yr. “We count on these tightness considerably be launched in subsequent yr, in all probability in direction of the tip of subsequent yr. […] I can’t provide the actual quantity [in terms of processed wafers capacity], however CoWoS [capacity will be doubled in 2024 vs. 2023].“
Supply: Nikkei
